WMMX Data Processing Result Penalty/Warning

XSCW_CDP_RES

Interpretation

The instruction uses the result of a WMMX data processing instruction as a source operand. The pipeline is stalled and the instruction takes additional cycles to execute until the result becomes available.

Advice

Reorder the instructions if possible to fill the extra delay cycles before the instruction using the register.

Note

This Penalty/Warning is only applicable to Intel® Wireless MMX^TM Instruction Set.

Example1

WMACU    wR4, wR5, wR7

WADDB    wR0, wR4, wR1    ;; XSCW_REG_wR4, XSCW_CDP_RES  

MOV         R4,  R1

Alternative

WMACU    wR4, wR5, wR7

MOV          R4,  R1

WADDB    wR0, wR4, wR1

Example2

WSUBBUS    wR4, wR2, wR9

WADDB      wR0, wR4, wR1  ;; XSCW_REG_wR4, XSCW_CDP_RES

Note

When saturation is specified for WADD or WSUB, the result latency is increased to 2 cycles.