LDRD - DSP InstructionLDR[condition]D dest, addr_mode
where:
|
condition |
One of 16 conditions. Refer to Condition Code Status. |
|
dest |
destination register; even numbered register followed by odd numbered register |
|
addr_mode |
Addressing Mode 3: Miscellaneous Loads and Stores |
|
basereg |
base register used by addr_mode |
A data abort exception is generated if an invalid load or store data access is attempted. An alignment exception is generated if a system control coprocessor is implemented with alignment checking enabled and an address where bits[01:0] != 0b00. An alignment exception may be generated if a system control coprocessor is implemented with alignment checking enabled and an address where bits[02:0] != 0b100; implementation defined. The load address must be doubleword-aligned.
|
N |
Z |
C |
V |
Q |
S |
I |
F |
T |
|
T |
T |
T |
T |
|
|
|
|
|
|
31 |
|
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
|
16 |
15 |
|
12 |
11 |
|
8 |
7 |
6 |
5 |
4 |
3 |
|
0 |
|
condition |
0 |
0 |
0 |
P |
U |
I |
W |
0 |
basereg |
dest |
addr_ mode |
1 |
1 |
0 |
1 |
addr_ mode |
||||||||||
1 @.text
2 @.globl funcldrd
3 @.align 0
4
5 @ * * * LDRD (Addressing Mode 3) * * *
6
7 AREA load_store, CODE, READONLY
8
9 00000000 E3A02014 MOV R2, #20
10 00000004 E3A03003 MOV R3, #3
11 00000008 E5823000 STR R3, [R2]
12 00000012 E3A05032 MOV R5, #50
13 00000016 E3A06006 MOV R6, #6
14 00000020 E5856000 STR R6, [R5]
15 00000024 E18240D5 LDRD R4, [R2, R5]
16
17 00000028 E3A0603C MOV R6, #60
18 00000032 E3A07007 MOV R7, #7
19 00000036 E5867000 STR R7, [R6]
20 00000040 E3A09009 MOV R9, #9
21 00000044 E0C680D9 LDRD R8, [R6], R9
22
23 END